发明名称 LOW LEVEL CLAMP CIRCUIT
摘要 PURPOSE:To keep an intermediate level to a prescribed level stably with high accuracy even when a characteristic variation due to power supply fluctuation or temperature change of a diode by clamping a low level of a multi-value level of three or more values. CONSTITUTION:A negative bias drive circuit 1 outputting a pulse having an amplitude in response to a power voltage and fed with a negative bias power supply and a drive circuit 2 whose power is supplied from the negative bias power supply via the 1st diode 4 and outputting a clock pulse having a level between a low level and an intermediate level to be stabilized at least are provided. Then the 2nd diode 6 clamping a high level of the output pulse from the negative bias drive circuit 1, a rectifying smoothing circuit using the 3rd diode 7 to rectify the output pulse subject to high level clamp, smoothing it by a capacitor 8 and obtaining a negative bias DC output and the 4th diode 9 clamping the low level of the clock pulse to the negative bias DC output level are provided.
申请公布号 JPS6282714(A) 申请公布日期 1987.04.16
申请号 JP19850223100 申请日期 1985.10.07
申请人 SONY CORP 发明人 MORI HIROSHI
分类号 H03K5/007;H03K5/08;H04N3/14;H04N5/335;H04N5/341;H04N5/357;H04N5/372;H04N5/378 主分类号 H03K5/007
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