| 摘要 |
PURPOSE:To attain accurate reading without using a clock of a reception signal by expanding/compressing the period of an internal timing, latching and retarding the result in response to the phase relation between the reception signal and the internal timing signal. CONSTITUTION:The edge of an external bit serial binary signal BS is detected (1) to obtain a pulse EP synchronously with the edge. A number 64 set to an entry device 3 is present in a counter 2 and a carry signal CRY is generated at 24 sets of clocks CLK each. The signal BS is read at each signal CRY in a FIFO register 7. The data read in the register 7 before is latched (12) by using a timing signal TS generated from a signal generating circuit 5. Since a U/D counter 4 applies U/D count to the signal CRY and a signal DP obtained by retarding a signal TS, the count result is coincident with the data stored in the register 7. The period of the signal TS is expanded/compressed in a manner to be before and after the signal CRY. Thus, accurate reading is applied without using an external clock. |
