A sampling clock phase correction circuit.

摘要

A sampling clock phase correction circuit comprises a video signal sampling clock generation circuit (3) for producing a sampling clock (CK) having a constant phase relation with a reference input signal (STHD), a phase detection circuit (5) for detecting the phase of the sampling clock (CK) and the phase of a video sync signal (HD), and a CPU circuit (6) for receiving a detection signal (DT) from the phase detection circuit and discriminating advance and delay of phase of the sampling clock (CK) with respect to the phase of the video sync signal (HD). The arrangement is such that, in operation, the phase of the reference input signal (STHD) of the clock generation circuit is controlled with the detection signal (DT) so that the phase of the sampling clock (CK) is changed and the video sync signal (HD) is corrected.