| 发明名称 |
Sampling clock generation circuit. |
| 摘要 |
<p>A sampling clock generation circuit comprises a phase comparison circuit (1), a loop filter (2), a voltage control oscillator (3) and a first frequency divider (5). A horizontal sync signal or composite sync signal (8) of the video signal is used as a reference input signal of the phase comparison circuit (1). </p> |
| 申请公布号 |
EP0218406(A2) |
申请公布日期 |
1987.04.15 |
| 申请号 |
EP19860307274 |
申请日期 |
1986.09.22 |
| 申请人 |
SEIKO INSTRUMENTS INC. |
发明人 |
TANAKA, FUMIHIRO;MATSUSHIMA, KENICHI;SHIMADA, YOSHIO;YAMAGUCHI, KANEO;WATANABE, SHINYA |
| 分类号 |
G06K15/12;G09G5/12;G09G5/18;H03L7/08;H03L7/081;H03L7/18;H04N5/14;H04N5/91;H04N5/932;H04N11/04 |
主分类号 |
G06K15/12 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
