| 摘要 |
A pipeline processing apparatus has a plurality of pipeline stages, each stage including a pipeline latch and a pipeline processing circuit. A pipeline bus serially connects the several pipeline stages such that input data supplied through an input unit can be serially transported through the several pipeline stages and finally to an output unit. To facilitate testing the pipeline processing apparatus and specifically the individual pipeline stages and the data passing through these individual stages independently of the pipeline processing cycle, there is provided a common bus coupled to the input unit, the output unit and selectively to each of the pipeline stages. A designated pipeline stage is selectively coupled to the common bus and to cause test data to be supplied to the designated pipeline stage and subsequently read out from the designated stage.
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