| 摘要 |
PURPOSE:To prevent latchup by a through-current and to reduce a dynamic current consumption by providing a timing control circuit giving the 1st and 2nd signals deviated for a prescribed time based on an input signal respectively to each gate electrode of a PMOS and an NMOS. CONSTITUTION:A delay circuit 61 outputs an output signal retarding an input signal V1 slightly and gives the signal to an OR gate 62 and an AND gate 63. The OR circuit 62 ORs the input signal V1 and the output signal of the delay circuit 61 and the result is given to a gate of a PMOS 3. The AND gate 63 ANDs the input signal V1 and the output signal of the delay circuit 61 and gives the result to a gate electrode of an NMOS 4. Since the PMOS 3 and the NMOS 4 are turned off simultaneously at a period T, the latchup due to a through-current is prevented and the dynamic current consumption is reduced. |
