| 摘要 |
PURPOSE:To generate a synchronizing signal independently of number of flags by adopting the constitution that a synchronizing signal is formed from a leading output detected by a flag detection circuit and a trailing output delayed by a delay circuit in all cases where number of flags is >=1. CONSTITUTION:Every time a flag is detected from a reception data, a detection circuit 1 outputs a pulse of 1-bit length. A delay circuit 2 retards an output pulse of the detection circuit 1 by bit number of a flag pattern. A both-extreme detection circuit 3 collates an output of the detection circuit 1 with an output of the delay circuit 2 logically, the 1st pulse outputted from the detection circuit 1 is used as a leading output and the trailing pulse outputted from the delay circuit 2 is used as a trailing output, they are fed to a synchronizing signal generating circuit 4. The synchronizing signal generation circuit 4 outputs a synchronizing signal while the leading output of the both-extreme detection circuit 3 is used as a start point and the trailing output is used as a stop point. |
