| 摘要 |
PURPOSE:To obtain a simple and economical phase synchronizing device by using a signal retarding one clock pulse and a frame pulse of one data signal among n-set of data signals as a common frame pulse. CONSTITUTION:A frame pulse of a transmission line selected optionally among n-set of transmission lines is delayed by a delay circuit 200. A write data is given from an input terminal 1i into each elastic store memory (i), a write clock pulse is given from an input terminal 2i and a frame pulse representing the write head phase is given from the input terminal 3i to each elastic store memory (i) respectively. On the other hand, to read each elastic store memory (i), a common read clock pulse 100a being an output of a buffer 100 and a frame pulse 100b representing the read head phase are given. Thus, an intra- office output data is outputted from output terminals 21-2n while a retarded phase delayed to an input frame phase from one selected transmission line is used as a reference phase. |
