DYNAMIC BIPOLAR INTEGRATED MEMORY DEVICE

摘要

This describes a sense latch for a bipolar dynamic array in which each cell is comprised of a capacitor and a pnp-npn transistor. Cell information is stored in the capacitor. The capacitor may be either a discreet capacitor or may be formed as part of the base node of the pnp transistor. The sense latch of the invention comprises a pair of cross coupled transistors coupled between a pair of capacitively loaded bit lines of the array with one of the bit lines being coupled to a data cell and the other being coupled to a reference cell. Means for precharging the bit lines to a fixed voltage level and means for reading the cell to charge one of the bit lines to a level greater than the precharge level and apply a differential signal to the latch are also provided so that during the reading cycle one of the transistors in the latch becomes turned on so that the voltage levels of both bit lines are determined by the characteristics of the turned on transistor only. The voltage on one line is determined by the forward base-emitter characteristics of the turned on transistor and the voltage on the other line is determined by the saturated collector-emitter characteristics of the same turned on transistor.