| 摘要 |
It is described a processor with a high throughput which executes operations in a pipeline system, comprising the following elements:… A group of operand registers (1) with a plurality of registers, and a pipelined arithmetic unit (3) with a plurality of operational stages. Outputs of the operational stages are used as operand inputs via a plurality of data buses (4) to the arithmetic unit (3). A selector circuit (2) select either an output from the group of operand registers (1) or that of the arithmetic unit (3). By means of a generator for generating an operand determination signal and a control circuit it is effected control as either to selectively give said group of operand registers (1) or the data buses (4) or, if said operands are not yet determined, to wait for the start of operation and to start operation as soon as said operands are determined by an operand register number designated by said another instruction, an operand determination signal corresponding to said operand stage of the arithmetic unit (3), a register number for designating said operand register to be renewed and for serving as operands for the group of operand registers (1), and a command to renew the contents of the operand register corresponding to the stage of the arithmetic unit (3). |
