| 摘要 |
<p>The equalizer comprises branching circuits (B) for branching a digital modulated signal into two outputs which are orthogonal to each other, at least three first weighting circuits (R) for weighting one of the outputs of the branching circuits (B) second weighting circuits (I) not greater in number than the first weighting circuits (R) for weighting the other of the outputs of the branching circuits. Combining circuits (A) equal in number to the first weighting circuits (R) combine two or three inputs. Delaying circuits (T) smaller in number than the combining circuits (A) by one, and the combining circuits (A) are interconnected sequentially and alternately. The outputs of the first weighting circuits (R) are respectively applied to the combining circuits (A) while those of the second weighting circuits (I) are respectively applied to selected ones of the combining circuits (A). In such an equalizer, the number of inputs to a combining circuit does not increase beyond a predetermined one despite any increase in the number of taps. </p> |
