发明名称 LOGIC CIRCUIT
摘要 PURPOSE:To suppress a through-current by providing an N type transistor (TR) whose gate and drain are connected between P type the 1st TR and N type the 2nd TR. CONSTITUTION:When the gate input signals of TRs QP1, QN1 changes from an H level to an L level, the potential of a gate S2 is a potential lower by the threshold value of the TR QN1 than the potential of the gate S1. When the signal S changes from an L level to an H level, the potential change of the gate S2 is faster than that of the gate S1, and since the timing when the TR QN2 is turned on by the gate S2 is faster than the timing when the TR QP2 is turned on by the gate S1, the time of simultaneous-on is reduced.
申请公布号 JPS6276320(A) 申请公布日期 1987.04.08
申请号 JP19850215326 申请日期 1985.09.27
申请人 NEC CORP 发明人 MIYATA SHINOBU
分类号 H01L27/088;H01L21/8234;H03K17/687;H03K19/00;H03K19/0948 主分类号 H01L27/088
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