发明名称 VESSEL FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain an economic vessel for an IC by Au-plating only on a necessary portion. CONSTITUTION:A substrate 1 and a conductor metal layer 7 are integrally baked, Ni-flash plated at 8, then selectively Au-flash plated at 9, and pins 12 are eventually Ag-brazed on a mount 6. The pins 12 are not Au-plated in this case. The thickness of the layer 8 of the layer 7 of a wire bonding portion 4 is set to a range of 0.01-0.5mum to prevent Au-plating from swelling at brazing time after Au-plating, and to prevent the conductivity of Au-plating due to diffusion of Ni to Au from deteriorating. With this configuration, the unnecessary use of Au can be reduced to obtain an economic vessel for an IC.
申请公布号 JPS6276744(A) 申请公布日期 1987.04.08
申请号 JP19850217573 申请日期 1985.09.30
申请人 NARUMI CHINA CORP 发明人 NAKANO SUMIO
分类号 H01L23/12;H01L23/498;H01L23/50 主分类号 H01L23/12
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