| 摘要 |
A semiconductor memory device includes at least a pair of bit lines, a word line, a pair of load transistors each connected to the bit lines, a memory cell connected to the bit lines and the word line and selected by an address signal, and an equalizing circuit connected between each of the bit lines. According to the present invention, the equalizing circuit comprises an P-channel type MIS transistor and an N-channel type MIS transistor that are connected in parallel and temporarily turned ON in response to a change of the address signal.
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