| 摘要 |
PURPOSE:To reduce remarkably a forming region of a transfer mold by using master slice so as to select a gate length of the transfer mold so as to very an ON-resistance optionally. CONSTITUTION:In selecting the width of a gate electrode 41 by the master slice so as to form the channel length as, e.g., L1, the on-resistance of an NMOS 35 is R1. Thus, the input signal is delayed for a prescribed time by a time constant R1.C1 comprising a capacitance C1 of a parasitic capacitor 39 and the on-resistance R1 and the result is given to an inverter 38. Thus, plural channel lengths L1-4L1 are prepared in advance and the channel lengths L1-4L1 and the gate electrode 41 are selected by the master slice, then the on-resistances R1-4R1 of the NMOS 35 are set optionally and a desired delay time is obtained. |
