| 摘要 |
PURPOSE:To attain accurately demodulation after a preamble period by switching a reply characteristic of a PLL at an optional period in response to the system characteristic to be applied. CONSTITUTION:A circuit comprising ROMs 33, 34, 1st and 2nd adders 36, 37 and a latch circuit 38 forms a digital loop filter. A multiplication coefficient alphaof a multiplier 41 corresponds to a coefficient of a proportional term in the response characteristic of the loop filter, a multiplication coefficient beta shown in a multiplier 42 corresponds to a coefficient of an integration term and taurepresents a delay time by a latch circuit 38. In changing values alpha, beta by a preamble period T2, and a data period T3 during the period T1 where the PLL is operated, the characteristic of a phase error signal 31a to a frequency is changed so that the PLL responds quickly during the preamble period T2 and the PLL shows a slow characteristic during the data period T3. The ROMs 33, 34 are used as means varying the alpha, beta. |
