| 摘要 |
PURPOSE:To increase the phase difference detection accuracy at the steady state of a PLL by adding a frequency divider controlling the frequency division ratio variably to a digital PLL circuit without increasing the bit number (n) processable at a counter circuit, a storage circuit and a signal processing section. CONSTITUTION:An output signal (c) of the 2nd frequency divider 3, whose frequency division ratio is variable, frequency-dividing an output of an oscillator 1 is inputted as a clock of the counter circuit 5 and the frequency division ratio of the 2nd frequency divider is varied by a signal (d) outputted from a signal processing section 7. When the phase difference between an output signal (b) of the 1st frequency divider 2 and the external signal (a) is small, that is, when the phase difference is DELTAT of below, the frequency division ratio of the 2nd frequency divider 3 is decreased and the period Tc of the output signal (c) is shortened as less as possible within the range satisfying Tc>DELTAT/2<n>. On the other hand, the period Tc and the phase difference detection accuracy of the signals (b,s) are inversely proportional. Thus, the phase difference detection accuracy is increased more by decreasing the period of the clock signal (c) at the steady-state of a PLL. |
