| 摘要 |
PURPOSE:To prevent latchup by a method wherein an inner logic P-well is positioned on the output terminal side and P<+> diffused regions connected to a power source is positioned at the end of the P-well. CONSTITUTION:A P-well 5 is positioned for an inner logic 7 on the side of an output terminal 1 and a plurality of P<+> diffused regions 6 connected to a VSS terminal are positioned at the end of the P-well 5 for the establishment of contact between the P-well 5 and a power source. When a voltage higher than a power source voltage VDD or a current is applied to the output terminal 1, a parasitic transistor TL1 base current runs through the output terminal 1 P<+> diffused region 2 N-bulk 3 N<+> diffused layer 4 VDD terminal. The transistor TL1 is then placed in an activated status, when a collector current runs through the output terminal 1 P<+> diffused region 2 N-bulk 3 P-well 5 P<+> diffused region 6 VSS terminal. In this process, with a collector current running toward the P-well 5 being promptly absorbed by the P<+> diffusion region 6, the base potential of a transistor TV1 is kept from rising, which suppresses latchup. |
