| 摘要 |
PURPOSE:To attain the same high speed conversion as that of a parallel type AD converter by adopting circuit constitution in which 2 series comparator groups in parallel for the comparison of low-order bits are provided and operating them alternately. CONSTITUTION:An input voltage Vin is compared with voltage division voltages VR1, VR2, VR3 between reference voltage VRH and VRL being applied to resistor- division by 3 high-order comparators 10 at the same time and a high-order 2-bit Du is obtained by an encoder 16. Further, the encoder 16 outputs a signal SEL selecting one of 4 switch groups 12, 13, 14, 15 based on the result of comparison of the comparator group 10. Then the input voltage Vin is compared simultaneously with each voltage division voltage from a switch group selected in advance by the signal SEL at 3 low-order comparators 11a or 11b and a low- order 2-bit DL is obtained via an encoder 17. The 2 series of the low-order comparator groups 11a or 11b are operated alternately synchronously with the high-order comparator 10 and the compared output is fetched to the encoder 17 alternately by a switch group (multiplexer) 18. |
