发明名称 |
Byte addressable memory for variable length instructions and data |
摘要 |
A random access memory having the capability to access one or more bytes in one or more memory word locations of a multi-byte memory array within one memory cycle. Variable length instruction and data words composed of multiple bytes are stored in a block of addressable locations in a memory so that individual bytes of each word are aligned in columns. Each column of bytes is addressable independently of the other byte columns via adders. A most significant bit portion of a memory location address is fed into a first input of column adders and the output of a first decoder circuit is fed into a second input of the adders for address incrementing within one memory cycle. A second decoder circuit generates a separate read or write enable line to each column of bytes. Both decoders are controlled by a least significant bit portion of the memory address and reference word byte size codes. A bi-directional multiplexer rearranges the order of the bytes so they appear in the proper order at the memory interface.
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申请公布号 |
US4654781(A) |
申请公布日期 |
1987.03.31 |
申请号 |
US19840665510 |
申请日期 |
1984.10.30 |
申请人 |
RAYTHEON COMPANY |
发明人 |
SCHWARTZ, MARTIN J.;HOWES, H. FRANK;EDRY, RICHARD J. |
分类号 |
G06F9/30;G06F9/38;G11C7/10;G11C8/12;(IPC1-7):G06F12/04 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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