发明名称 PLL DEVICE
摘要 PURPOSE:To eliminate the influence of the drift of a low-pass filter, to improve the accuracy of a clock pulse and to ensure the correctness of phase locking by comparing directly the phase of a horizontal phase locking signal and the clock pulse in a video signal after the quantization. CONSTITUTION:A video signal 71 inputted from an input terminal 41 is converted through a buffer amplifier 42 to a video signal 72 of a low impedance and supplied to a low-pass filter 43 and a phase lock separating circuit 45. Through an A/D converter 44, a pulse generator 47, an arithmetic circuit 52, latch circuits 48-51, etc., the first PCM data 76 and the second PCM data 82 are outputted to an arithmetic circuit 55 and from the circuit 55, the third PCM data 83 are outputted. The data 83 return to the analog signal by a D/A converter 56, controls the oscillating frequency of an oscillating device 46 and the feedback loop is operated so as to make the data 83 into 0. Thus, the phase is coincident to the phase locking signal of a video signal 73 and the frequency of a horizontal phase locking pulse 81, the accuracy of a clock pulse 75 can be improved and the phase can be correctly locked.
申请公布号 JPS6269776(A) 申请公布日期 1987.03.31
申请号 JP19850209458 申请日期 1985.09.20
申请人 NEC CORP 发明人 TAKIMOTO HIDEKI
分类号 H03L7/06;H04N5/06;H04N5/12;H04N7/24 主分类号 H03L7/06
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