Transistor-transistor logic to emitter coupled logic translator

摘要

A transistor-transistor logic (TTL) to emitter coupled logic (ECL) translator includes a TTL input gate for receiving TTL voltage level logic input signals in the positive voltage range compatible with TTL circuits and an ECL output gate for delivering corresponding ECL voltage level logic output signals in the negative voltage range compatible with ECL circuits. A translating current source operatively coupled between the TTL input gate and ECL output gate translates signals down to the negative ECL voltage range for application to the input transistor of the ECL output gate. A bidirectional bridge clamp also operatively coupled between the TTL input gate and ECL output gate limits the swing of the translated signals in the negative voltage range applied at the input of the ECL output gate thereby reducing propagation delay across the translator and reducing power dissipation.