发明名称 PHASE SYNCHRONIZING OSCILLATOR
摘要 PURPOSE:To prevent the generation of out-of-phase synchronization at the changeover of an active/standby exernal reference signal by adding a phase synchronizing oscillator having a digital phase comparator applying buffering operation against the changeover of active/standby input reference signal to the pre-stage of a conventional analog phase comparator. CONSTITUTION:A main voltage controlled oscillator 1, an analog phase compara tor sampling phase detector (SPD) 2 and a loop filter 3 constitute an analog phase locked loop and its reference signal is an output of a voltage controlled crystal oscillator 4. The voltage controlled crystal oscillator 4, a digital phase comparator 5 and a loop filter 6 constitute a digital phase locked loop and its reference signal is inputted externally. The external reference signal source consists of an external reference signal source active device 7 of the same frequency, an external reference signal source standby device 8 and a change over switch 9. The band characteristic of the digital phase locked loop is lowered sufficiently than the band characteristic of the analog phase locked loop of a main phase synchronizing oscillator so as to apply sufficiently slow pull-in even when a step change exists in the frequency and phase of the input reference signal at the changeover of an active/standby device.
申请公布号 JPS6267927(A) 申请公布日期 1987.03.27
申请号 JP19850207142 申请日期 1985.09.19
申请人 NEC CORP 发明人 NAGATA EIJI;HAGA ISAO
分类号 H03L7/10;H03L7/06 主分类号 H03L7/10
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