| 摘要 |
<p>A hybrid hardware/software implementation of a translation look-aside buffer (TLB) is disclosed for improving the efficiency of address translation in a computing system utilizing a virtually addressed memory. Through the use of the present invention, complex hashing routines can be used to address entries in a virtual address translation table (VSTT) within the system's physical memory, without increasing the complexity or significantly reducing the performance of the TLB fetch hardware. </p> |
