| 摘要 |
PURPOSE:To improve the degree of integration, and to enhance the holding characteristics of information by forming capacity electrodes as being divided at every memory cell while applying predetermined potential by wirings for feed connected to the upper surfaces of the capacity electrodes. CONSTITUTION:A dielectric film 2 for a capacity element, a p-type semiconductor region 4A and an n<+> type semiconductor region 5A are shaped to the surfacer of a substrate 1. A polycrystalline silicon film 6 is formed on the whole surface on the substrate 1, and patterned into a pattern in which two bits are unified by using resist marks 7. The exposed dielectric film 2 and the substrate 1 are etched, and grooves 8 are shaped. p-type channel stopper regions 9 are formed on the surfaces of the substrates 1 in the bottoms of the grooves 8, and silicon oxide films 10 are buried into the grooves 8 and shaped on the whole surfaces on the substrates 1. Element isolation insulating films 10A are formed through etching from upper surfaces. A polycrystalline silicon film 11 and a resist mask 12 having a pattern in which regions in which MISFETs are shaped are exposed are formed on the whole surface on the substrate 1, and the polycrystalline silicon film 11 is etched, thus completing wirings for feed. |
