Method of fabricating a junction field effect transistor utilizing epitaxial overgrowth and vertical junction formation

摘要

Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions. Each gate region has portions extending laterally between the adjacent barriers and the underlying strip to form a gate junction between each portion and the N-type silicon of the second epitaxial layer. N-type conductivity imparting material is ion implanted into the intervening zones to form source regions. Metal contacts are applied to the gate regions, the source regions, and the substrate.