| 摘要 |
PURPOSE:To shorten memory access time, by suppressing the movement of one block and sending out only necessary data to a CPU through a bypass when block crossing occurs. CONSTITUTION:Since a data block crosses the block boundary in a buffer memory if a carry signal is detected when the lowest order bit and length of an address set in a buffer memory address register 1 are added to each other at a comparator C5, the carry signal of the comparator 5 is used to control the input gate G of a data section 4 so that the writing operation of the data section 4 can be inhibited and only data required by a CPU can be sent directly to the CPU through a bypass route BPR, when the data block does not exist in a buffer memory but is transferred from a main storage device. |
