发明名称 |
Circuit arrangement for performing rapid sortation or selection according to rank |
摘要 |
The invention is directed to a circuit arrangement for rapid sortation or selection of at least three digital values according to rank. In the circuit arrangement, the input channels are directly interconnected via digital comparators or arithmetic logic units. The outputs of the digital comparators or arithmetic logic units are connected to a gate-logic circuit or a ROM table controlling data selectors for the transfer of selected values or a network of data selectors for the sortation of all input values.
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申请公布号 |
US4651301(A) |
申请公布日期 |
1987.03.17 |
申请号 |
US19840620130 |
申请日期 |
1984.06.13 |
申请人 |
CARL-ZEISS-STIFTUNG |
发明人 |
BALLMER, HORST;KRAEMER, HENRY |
分类号 |
G06F7/24;(IPC1-7):G06F7/00 |
主分类号 |
G06F7/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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