发明名称 FABRICATION PROCESS- FOR A DIELECTRIC ISOLATED COMPLEMENTARY IC
摘要 25307-122 An improved method for fabricating an isolated region for dielectric isolated complementary IC is disclosed. In order to avoid the difficulty of mask alignment and patterning on a deep etched uneven surface of the substrate, the present invention intends to align the pattern before etching. The etching to form the p-type and n-type islands on the surface of the substrate is done at the same time. Next on the surface of the substrate is grown a polysilicon layer. Then the substrate is lapped off from its back surface and removed, leaving the island parts in the polysilicon layer, which becomes a new substrate. FP-56045/T53
申请公布号 CA1219379(A) 申请公布日期 1987.03.17
申请号 CA19840465141 申请日期 1984.10.11
申请人 FUJITSU LIMITED 发明人 TANI, SATORU
分类号 H01L29/78;H01L21/331;H01L21/74;H01L21/76;H01L21/762;H01L21/8222;H01L21/8228;H01L27/08;H01L27/082;H01L29/73 主分类号 H01L29/78
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