| 摘要 |
<p>PURPOSE:To reduce sharply the number of multipliers and to attain high speed arithmetic processing by using 11 multipliers and 29 adders for a reference unit and executing specific matrix operation. CONSTITUTION:The formula 1 shows the block diagram of a device indicating the flow of a discrete cosine transform (DCT) signal. The device is constituted of 20 adders (A1-A20 and adders included in Y1-Y3), 11 multipliers (M1, M2 and multipliers included in the Y1-Y3) and 16 code inverters (P0-P10 and code inverters included in the Y1-Y3) and the number of multipliers is especially reduced. Consequently, arithmetic processing algorithm is simplified in addition to the simplification of the device constitution to attain high speed arithmetic processing.</p> |
