发明名称 ARTIFICIAL TROUBLE GENERATING CIRCUIT
摘要 PURPOSE:To easily take a test by generating an error due to artificial trouble when an operation request whose address coincides with an artificial trouble address arrives. CONSTITUTION:When an artificial setting signal is inputted to a signal line 11, an artificial trouble setting circuit 1 holds its contents and outputs an artificial trouble signal to a signal line 13 at the same time. Further, when an artificial address setting signal is inputted to a signal line 12, an artificial trouble address setting circuit 2 holds its contents and outputs an artificial trouble address to a signal line 14. An artificial trouble address comparing circuit 3 compares a specified address from a signal line 15 with the artificial address from the signal line 14 and outputs an address coincidence signal to a signal line 16 when they coincide with each other. When three kinds of signals, i.e. the artificial trouble signal from the signal line 13, the address coincidence signal from the signal line 16, and the operation request signal from a signal line 17 are inputted to an artificial trouble error generating circuit 4, the circuit 4 outputs an artificial error signal to a signal line 18.
申请公布号 JPS6260036(A) 申请公布日期 1987.03.16
申请号 JP19850200221 申请日期 1985.09.10
申请人 NEC CORP 发明人 YAMAUCHI MAKOTO
分类号 G06F11/22 主分类号 G06F11/22
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