发明名称 METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PURPOSE:To easily detect a defect memory cell in terms of leakage by alternately selecting a written test cell and an unwritten real cell and deciding the defective real cell or good one from the access time of the real cell. CONSTITUTION:When the test cell Mt is selected, a bit line potential V is VL. When the selected cell is switched to the real cell M0, the bit line potential rises to VH. If the selected real cell M0 is a good cell sufficiently being off, the potential rises from VL to VH quickly as shown in a curve C1, but if the real cell is defective one having a leak, the rise is delayed. Therefore the defective cell can be decided by checking the potential from the point when a memory access address is switched up to the appropriate time ts and deciding whether the potential is high or low, compared with a threshold of, for example, TL. The curve C1 means a good cell, whereas a curve C2 means a defective cell. In this way a slight leak of the defective cell can be easily detected, whereby a writing efficiency and a characteristic guarantee accuracy after writing can be improved.</p>
申请公布号 JPS6258500(A) 申请公布日期 1987.03.14
申请号 JP19850198761 申请日期 1985.09.09
申请人 FUJITSU LTD 发明人 FUKUSHIMA TOSHITAKA
分类号 G11C17/00;G11C29/00;G11C29/04;G11C29/24;G11C29/50 主分类号 G11C17/00
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