| 摘要 |
PURPOSE:To reduce the plane occupied area of an FET by arranging source and channel drain regions to each Si layer laminated through an insulating layer. CONSTITUTION:The SiO2 22 with an opening 33, an N type Si layer 23, SiO2 24 opposite to the opening 33 and a P type Si layer 25 are laminated onto a P type Si layer 21. An N<+> layer 26 is formed near the window 33 of the P layer 21 and used as a source electrode 30, and an N<+> layer 29 is shaped near the window 34 of the P layer 25 and employed as a drain electrode. P layers 27, 28 are formed to the N layer 23, and used as the gate electrode 34. A semiconductor layer is shaped through a CVD method, and the insulating layer is obtained through oxidation treatment or the evaporation of an insulator. According to this constitution, the FET can be arranged at high density. |
