| 摘要 |
A data processing system is described comprising a cyclic bulk storage device attached to a CPU and a main storage through standard channel facilities including a channel control unit. The storage device is divided into a plurality of randomly accessible pages each page being subdivided into two sequentially and cyclically accessible Sectors 0 and Sector 1. Data is transferred byte by byte between a selected page of the device and a specified one-page data area (labelled Real Page) in the main storage. A channel program is constructed using three channel command words (CCWs); a Seek Page command (CCWI) followed by two different Read or Write commands CCW2, CCW3. At the end of the Seek Page operation, (CCWI) the control unit determines which of Sector 0 or 1 is more immediately accessible. If it is Sector 0 a branching control signal given to the channel causes the channel to chain to the second command CCW2, but if it is Sector 1, a different control signal given to the channel causes it to skip over the second command CCW2 and chain to the third command CCW3. When chained to the second command CCW2, the channel executes the transfer of one page of data in normal sequence, i. e. Sector 0 first and Sector 1 next. When chained to the third command CCW3, the channel executes the data transfer in reverse sequence, i.e. Sector 1 first and Sector 0 next. Such sector transfers are selectively controlled by indirect data address words (IDAWs) addressed by addresses IDAW1 and IDAW2 contained in the commands CCW2 and CCW3. Following transfer of a complete page, the control unit generates a signal combination causing the channel to chain to a first command CCW1 in a second program of three commands CCW1, 2 and 3. |
