| 摘要 |
PURPOSE:To prevent an error produced from an error signal by using means to produce the 1st speed error signal, an input capture register to store the count value a counter, a means to produce the 2nd speed error signal and a means to keep the processing of the 2nd speed error signal producing means in a waiting state. CONSTITUTION:A timer counter 150 counts the reference clock signals and is reset or preset with the timing of a reference phase signal. The 1st speed error signal producing means 151 produces the 1st rotation control signal (the 1st speed error signal) based on the count value of the counter 150 and with the timing of the 1st revolution detecting signal (the 1st GF signal, i.e., the FG signal of a head motor). An input capture register 152 stores the the count value of the counter 150 with the timing of the 2nd revolution detecting signal (the 2nd FG signal, e.g., the FG signal of a capstan motor). The 2nd speed error signal producing means 153 supplies the 2nd revolution detecting signal and produces the 2nd revolution control signal (the 2nd speed error signal) based on the value stored in the register 152. A priority means 154 gives the higher priority to the processing of the means 151 than the processing of the means 152 and keeps the processing of the means 152 under a waiting state. |
