发明名称 LOGICAL SIMULATION SYSTEM
摘要 PURPOSE:To check easily and quickly the result of simulation by adding test circuit data and an output expected value to input data to produce both output data of the simulation result and check result. CONSTITUTION:A simulator 10 generates not only a simulation object circuit but also its check circuit. The check circuit corresponds to a check processing section and then it is not required to connected the check processing section to the post-stage of the simulator 10, and a simulator output S4 includes both the simulation result and check result. The input to the simulator 10 is a synthesis circuit data D5 between an output data D1 of a simulation object circuit and data D4 representing the check position and check content inputted to a check circuit generating section 16, input signal data D2 and an expected value signal S2 as the result of simulation. The result of check is outputted from the simulator 10 as an output S4 together with the simulation result.
申请公布号 JPS60124745(A) 申请公布日期 1985.07.03
申请号 JP19830232530 申请日期 1983.12.09
申请人 FUJITSU KK 发明人 ITOU YASUKAZU;SATOU NOBUYUKI
分类号 G01R31/28;G06F11/25;G06F11/26;G06F17/50 主分类号 G01R31/28
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