发明名称 CLOCK SWITCHING CONTROL SYSTEM
摘要 <p>PURPOSE:To avoid such a case where the clock switching action is not secured owing to a transient phenomenon produced in a clock switching mode, by providing a means to monitor the working state of the system, a means to suppress the system working, a means to give a switching instruction to a clock supply source for switching clock cycles and a means to release said suppression mode. CONSTITUTION:The working of a processor 2 is suppressed despite a request given for transfer of data with an information processing unit 5 if a communica tion display flag 41 is read out and at the same time logic '1' is set to a com munication suppression flag 12. It is checked whether data are transferred or not with an information processing unit 6 within a program to be executed by the processor 2 after logic '0' is set if the flag 41 is kept at logic '1' in an under-processing state or immediately the flag 41 is kept at logic '0' respec tively. Then the transfer of data is suppressed with the unit 6 in the same way. In such a way, the processor 2 gives an instruction to a clock supply unit 3 to change the cycle of a clock 34 after suppressing the transfer of data.</p>
申请公布号 JPS6255718(A) 申请公布日期 1987.03.11
申请号 JP19850195250 申请日期 1985.09.03
申请人 NEC CORP 发明人 MOMOSE HIRONARI
分类号 G06F1/08;G06F1/04;G06F11/22 主分类号 G06F1/08
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