Error-correcting circuit having a reduced syndrome word

摘要

An error-correction circuit for correcting up to one error in an M-bit data field having the conventional number K parity bits associated with it uses a syndrome word having K-1 bits. The data elements are ordered sequentially and the K-1 bit syndrome word points to errors in the data only, not to errors in the parity bits. One of the data addresses in the field is reserved as a no-error flag and a Kth parity check bit associated with the syndrome word flags an error in the parity bits.