| 摘要 |
PURPOSE:To shorten a smapling cycle to an analog signal by using plural pairs of sample holding circuits and sequential comparison type A/D converters to form a circuit. CONSTITUTION:The 1st sample holding circuit 5 is combined with a sequential comparison type ADC7 to convert an input analog signal into a digital signal after amplifying the analog signal by an amplifier 1. The digital signals are delivered every double cycle 2Ts. The combination of the 2nd sample holding circuit 6 and a sequential comparison type ADC8 is actuated with a delay by a campling cycle Ts2 compared with the 1st combination of the circuit 5 and the ADC7. Thus the digital signals are delivered every 2Ts. A selector 9 switches output every cycle Ts2 between the ADC7 and ADC8 to obtain output digital signals 20(D0-Dn). |
