| 摘要 |
PURPOSE:To detect the synchronizing pattern by providing a circuit holding and senting a parallel signal based on a clock signal subjected to frequency division to a circuit converting an input data signal into a parallel signal. CONSTITUTION:A synchronizing pattern detection circuit 6 compares a frame pattern inputted from a frame pattern generating circuit 7 with a parallel data signal to detect whether or not a synchronizing pattern is coincident at the location of a frame location signal inputted from a frame counter 8. When the synchronizing pattern of the input data signal differs depending on the location of a frame pulse by a location signal from the frame counter 8, a dissidence pulse is sent to a 1/N frequency division circuit 4. When the 1/N frequency division circuit 4 receives a dissidence pulse, since the clock is stopped, the phase of the output in the holding circuit 10 is shifted, the output phase of the circuit 10 is being shifted until the synchronization is attained. Thus, the synchronizing pattern detection circuit is constituted by a low speed element. |
