| 摘要 |
PURPOSE:To obtain a delay data generator with less memory capacity by providing the 1st memory storing data by a data number, the 2nd memory storing the data number and the 3rd memory storing data outputted after a prescribed time. CONSTITUTION:The data number from a control circuit 1 is given to the 1st memory 2 storing data and 2nd memory 3 storing the data number. The memory 2 used the number as an address to read the data and outputs it from a terminal 10. The memory 3 receives the data number as write data and stores it in a write address increased by 1 at each clock period T. A data delay time nT is stored in a register 6 for the (n), a subtractor 7 subtracts the value of the register 6 from the value of the counter 5 and the value is given as the read address of the memory 3. The memory 3 gives the data number given from the circuit 1 to the 3rd memory 4 after the time nT and the similar data as that in the memory 2 is outputted from a terminal 11 of the memory 4 after the time nT. Thus, the memory capacity required for the delay is less. |
