| 摘要 |
PURPOSE:To easily detect the abnormality of a bus by letting a test pattern generating part output a test pattern when a try state bus is at a high impedance and comparing said pattern with a try state driver output. CONSTITUTION:Until the try state bus 4 becomes a high impedance, a test timing generating part 2 outputs an output permission signal to a try state driver 1. Moreover, said part 2 outputs to the test pattern generating part 3 the timing when the test pattern is changed, and simultaneously outputs to an FF circuit 7 the timing when the abnormality is detected and held. The test pattern generating part 3 outputs the test pattern to the try state driver 1 at every test. Since the try state driver 1 is in a state where it is permitted to output, it outputs the pattern to a receiver 5 when the try state is normal, and compares said state with the test pattern. If the compared result is not equal because of the abnormality of the try state driver 1 or the bus 4, the FF circuit 7 maintains the result. |
