发明名称 FRAME SYNCHRONIZING SYSTEM
摘要 <p>PURPOSE:To improve transmission efficiency without the need of the transmission of a frame synchronizing signal separately from a data signal by using in common a parity check bit for the detection of frame synchronizing position. CONSTITUTION:A signal series whose frame consists of a 1 word data comprising plural bits and its patiry check bit is sent from a transmission side. A reception signal is inputted to a pattern detection circuit 13 comprising the cascade connection of shift registers 14-1, 14-2 having 1-frame of word length is inputted at the reception side. Then the parity check circuit 12 applied parity check to a data series in the shift registers 14-1, 14-2 of each stage every time of one bit shift. When no parity error exists as to all of the shift registers 14-1, 14-2 of each stage, it is detected as the frame synchronizing location.</p>
申请公布号 JPS6253039(A) 申请公布日期 1987.03.07
申请号 JP19850191839 申请日期 1985.09.02
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 IRIE KAZUNARI;KO MASAHIRO
分类号 H04J3/06;G06F11/10;H04L7/02;H04L7/08 主分类号 H04J3/06
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