发明名称 |
DIGITAL DATA CODE CONVERSION CIRCUIT FOR VARIABLE WORD-LENGTH DATA CODE |
摘要 |
In a preparation circuit(3) an input variable-word-length code of not more than N0 bits, where N0 equals 16, is divided into codes having word-lengths of not more than N1 bits, where N1 is less than N0 and is eight. Thus for N1 equal to 15, one word of 8 bits and a second word of 7 bits are output. These two words are input to the data code decoder(4). The converter assembles the words input ot it into 8 bit words and outputs them(DO1---DOn1). The data code converter is operated at a rate which is proportional to the data input rate times the number of divisions of the variable-word-length codes. |
申请公布号 |
KR860001344(B1) |
申请公布日期 |
1986.09.15 |
申请号 |
KR19830002965 |
申请日期 |
1983.06.30 |
申请人 |
JAPAN TELECOMUNICATION CO.,LTD.;FUJTSU CO.,LTD. |
发明人 |
KUROTA HIDEO;MUKAWA NAOKI;MATSUTA KIICHI;HONMA TOSHIHIRO;FUKUTA HIROSHI |
分类号 |
H03M7/40;G06F7/00;H03M5/14;H03M7/00;H04L25/49 |
主分类号 |
H03M7/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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