| 摘要 |
<p>PURPOSE:To attain the simulation of the process of signal processing by using a clock phase-locked to an output side clock and having a frequency by N-time as the signal processing clock of a bit buffer. CONSTITUTION:An input data is latched to a D-FF 17 at the trailing of the clock having a frequency twice that of a data clock f0. The they are latched by a D-FF 19 at the leading of the data clock f0. The output of the D-FF 19 is latched by a D-FF 20 at the leading of the output of a D-FF 16, that is, at the latter part of the H level of the clock f0 and the leading of a clock 8f00 phase-locked to the output clock f00 and having a speed by 8 times. Since the clock used in the process of the internal signal processing and the clock of the output data are phase-locked in the bit buffer circuit, the buffer is built in the inside of an LSI and simulated.</p> |
