发明名称 TEST SYSTEM FOR INFORMATION PROCESSOR
摘要 PURPOSE:To shorten the processing time by executing the test instruction on the host processor and checking the test result by the auxiliary processor after CPU is set to the test executable condition. CONSTITUTION:'SET G0=1' is executed by a maintanance diagnosing processor 22, and a G0 register built in a CPU 12 is set to 1 through a maintenance diag nosing interface 3. In the same way, the value of a G1 register of the CPU 12 is set to 2 by 'SET G1=2'. Next, when 'TST G1=G0+G1' is executed by the processor 22, the test instruction of 'G1=G0+G1' is set to a main mem ory device 11 through an interface 3, and the instruction is processed. Continuous ly, when 'CHECK G1=3?' is executed by the processor 22, the contents of a G1 register of the CPU 12 are read through the interface 3. When the read value is not 3, the message of the trouble detecting report is outputted to the displaying device equipped with the device 2.
申请公布号 JPS6250937(A) 申请公布日期 1987.03.05
申请号 JP19850191230 申请日期 1985.08.30
申请人 NEC CORP 发明人 TSUCHIYA KITSUYA
分类号 G06F11/22 主分类号 G06F11/22
代理机构 代理人
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