发明名称 COMPOSITE SYNCHRONIZING SIGNAL SEPARATION CIRCUIT
摘要 PURPOSE:To easily isorate a vertical synchronizing signal from the pulse state of a composite synchronizing signal by counting clock pulses and driving a circuit digitally generating fixed time with the aid of the pulse fo the composite synchronizing signal. CONSTITUTION:A 'high' part included in the composite synchronizing signal is of 4.6-4.8 musec except for a vertical synchronizing signal part. Accordingly counters 6 and 7 and a flip flop 1 generate a digital one shot, and expand the 'high' part in the composite synchronizing signal to about 6.4 musec. When the signal samples the composite synchronizing signal again, the vertical synchronizing signal VD is extracted. Only the signal VD cannot identify a field. However, by exploiting that seven pulse strings with 1/2 H widths exist after the vertical synchronizing signal in the 1st field, the seventh string is identified to identify the top of a frame.
申请公布号 JPS62262582(A) 申请公布日期 1987.11.14
申请号 JP19860106124 申请日期 1986.05.09
申请人 FUJITSU LTD 发明人 SASAKI SHIGERU;OZAKI NOBORU;SATO TATSUYA
分类号 H04N5/10 主分类号 H04N5/10
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