| 摘要 |
<p>PURPOSE:To prevent the overlap of a two-phase clock by installing a clock generator for generating the multiphases clock of non-overlap from a fundamental clock at every function block and supplying the fundamental clock in accordance with the sequence of a data processing. CONSTITUTION:The sequence of a data processing in a signal processing LSI is executed in order of function blocks A-F, ad the wiring of a fundamental clock phiM is also performed in order of the function blocks A-F. With respect to the function blocks A-F, clock generators 10A-10F are installed, and each clock generator 10A-10F has a sufficient driving capacity against each function block A-F. Also, in said each function block A-F, a data is inputted by a two-phase block phi1, and a data is outputted by phi2 in the same way. In this way, the delay of the fundamental clock phiM in, for instance, the function block C and D is determined by a small wiring capacity and a small wiring resistance between the function block C and D, a delay between adjacent function blocks of the fundamental clock phiM is small, and the delay of two-phase clocks phi1, phi2 is also small.</p> |
