发明名称 Vertical contour emphasis de-emphasis circuit
摘要 Disclosed is a circuit for emphasizing a video signal in the vertical direction of a television picture for minimizing noise appearing during reproduction. In the circuit, a signal obtained by delaying an input video signal by one horizontal scanning period is positively fed back through a feedback circuit to the input of the input video signal. An amplitude difference signal between the video signal after being fed back through a positive feedback loop and the delayed video signal is produced and added to the input video signal to provide an output video signal.
申请公布号 US4647960(A) 申请公布日期 1987.03.03
申请号 US19850777288 申请日期 1985.09.18
申请人 HITACHI, LTD. 发明人 MIURA, KUNIAKI;YUNDE, YASUFUMI;KOTANI, KAZUNORI;FUKUSHIMA, ISAO;KANO, KENJI
分类号 H04N5/21;H03G7/00;H04N5/14;H04N5/205;H04N5/922;H04N5/923;H04N9/64;(IPC1-7):H04N5/208 主分类号 H04N5/21
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