| 摘要 |
PURPOSE:To optimally perform a pattern layout by an automatic design or a design by a computer by providing power source wirings on a metal wiring layer different from a signal wiring layer to reduce the size of a chip and a wiring capacity. CONSTITUTION:The cell array region of a chip 1 is divided into four sections 3-6, exclusive signal wiring regions 7-12 between the cell array regions opposed between the sections are formed, power source wirings 35-37 for applying a voltage to a logic circuit cell are formed on between the cell array regions and on the outer peripheral region to complete a logic circuit. Thus, a wiring pattern set to apply a voltage to the cells can be contracted to reduce the cell size, thereby improving the speed performance by decreasing the wiring capacity. The logic circuit itself to be placed is divided corresponding to the cell array regions to optimally dispose the cells when considering an automatic cell disposition by a computer and wirings between the cells, thereby reducing the wiring capacity. |
